Tuesday, December 06, 2011 | Barry Olney, In-Circuit Design Pty Ltd.
Editor's Note: This column originally appeared in the October 2011 issue of The PCB Magazine.
A differential pair is two complementary transmission lines that transfer equal and opposite signals down their length.
The debate rages as some argue that since the two halves of the pair carry equal and opposite signals, a good ground connection is not required as the return current flows in the opposite signal. In addition, tight coupling between the signals is better than loose coupling, as it reduces undesirable coupling from aggressor signals.
Others say that beyond the fact that differential pairs transfer equal and opposite signals, there are no special requirements that need to be considered when using differential pairs. They should be treated as two single-ended signals. The signals of a differential pair don’t need to be routed together, should not be tightly coupled and are not required to be routed to the differential impedance.
Hmm…I am not getting into this argument. As I look at PCB design from a practical designer’s point of view, the theory can be left to the experts to discuss.
However, most agree on the advantages of differential signaling:
- The ground (reference) connection between the driver and load can be poor and the signal quality will not be compromised.
- The signal can be attenuated significantly (20 dB) and still function properly.
- Because of the high noise immunity, they can carry extremely high data rates (10 Gb/s) compared to single-ended transmission lines.
- The equal and opposite nature of the differential pair means that demand on the power distribution network is less than for a similar single-ended data path.
Keeping both points of view in mind, I consider that symmetry is the key to successfully deploying differential signals in high-speed designs. Maintaining the equal and opposite amplitude and timing relationship is the principal concept when using differential pairs.
Differential pairs also require matched length traces. For instance, DDR2 clocks need to be matched to within 25 MIL. This ensures that there is no skew between the signals of the pair, and flight times will be identical, which is an important factor.
To control crosstalk, keep aggressor signals as far away as possible from differential pairs, especially in Microstrip (outer layers). A good rule of thumb: Clearance = 3 x trace width.
Additionally, reducing the signal layer to reference plane spacing (dielectric) improves crosstalk.
If the routing is dense then consider setting the clearance design rules to 2 x trace width to start. There is a good feature in Altium Designer that I use frequently: the “Parallel Segment” rule. This enables you to set a gap of 4 MIL (on the same layer or adjacent layer) for a maximum length of 500 MIL; then, the spacing must increase to 8 MIL.