This column originally appeared in the May issue of The PCB Magazine.

Today’s high-performance processors, with subnanosecond switching times, use low DC voltages with high transient currents and high clock frequencies in order to minimize the power consumption and hence, heat dissipated. Fast rise times, low output-buffer impedance and the simultaneous switching of busses create the high transient currents in the power and ground planes, degrading performance and reliability of the product. Inadequate power delivery can exhibit intermittent signal integrity issues. Also, many failures to pass electromagnetic compliancy (EMC) are due to excessive noise on the PDN coupling into external cables and radiating emissions.

A typical high-speed design, incorporating DRR3 memory, contains five or six individual power supplies. The PDN must accommodate these variances of current drawn with as little change in power supply voltages as possible (5% voltage ripple is a typical requirement). So the goal of PDN planning is to design a stable power source, taking the above into account, for all the required power supplies. Ideally, the effective impedance of the PDN should be kept as low as possible, up to the maximum operating frequency.

PDN planning is a trade-off of cost/performance and results in the following:

• Gives higher confidence in the performance and reliability of the product
• Meets the performance target at the lowest cost of production
• Finds and eliminates issues early in the design cycle

As with stackup planning, the PDN design is required before a single IC is placed on the board.

 

 Figure 1. PDN topology.

Figure 1 shows the topology of the PDN which includes the VRM, bulk bypass and decoupling capacitors, the plane, the die capacitance, plus BGA via and via spreading inductance.